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| TS8405P - single p-channel 1.8v specified microsurf? general description taiwan semiconductor?s new low cost, state of the art microsurf? lateral mosfet process technology in chipscale bondwireless packaging minimizes pcb space and r ds(on) plus provides an ultra- low qg x r ds(on) figure of merit. absolute maximum ratings t a =25c unless otherwise noted symbol parameter ratings units v dss drain-source voltage -12 v v gss gate-source voltage + 8v i d drain current ? continuous -4.9 a ? pulsed -10 p d power dissipation (steady state) 1.5 w t j , t stg operating and storage junction temperature range -55 to +150 oc thermal characteristics r ja thermal resistance, junction-to-ambient 85 c/w r jr thermal resistance, junction-to-balls 12 microsurf? for load switching and pa switch patent pending features ? -4.9a, -12v r ds(on) =50m ? at -4.5 volts ? -4.4a, -12v r ds(on) =70m ? at -2.5 volts ? -4.0a, -12v r ds(on) = 90m ? at -1.8 volts ? low profile package: less than 0. 8mm height when mounted on pcb. ? occupies only 2.25 mm 2 of pcb area. less than 25% of the area of a ssot-6. ? excellent thermal characteristics. ? lead free solder bumps available. preliminary data sheet for information only bump side view 1 9/14/03 rev5 dd g s
electrical characteristics t a =25c unless otherwise specified preliminary data sheet 2 i ds s zero gate voltage drain current v ds =-12v, v gs =0v -1 a zero gate voltage drain current v ds =-12v, v gs =0v, t=70c -5 a i gss gate-body leakage v gs =8v, v ds =0v 100 na v gs(th) gate threshold voltage v ds =v gs , i d =-250a -0.7 v drain-source on-state resistance v gs =-4.5v, i d =-1a 50 m ? drain-source on-state resistance v gs =-2.5v, i d =-1a 70 m ? drain-source on-state resistance v gs =-1.8v, i d =-1a 90 m ? c is s input capacitance v ds =-12v, v gs =0v, f=1mhz 800 pf c oss output capacitance v ds =-12v, v gs =0v, f=1mhz 250 pf c rs s reverse transfer capacitance v ds =-12v, v gs =0v, f=1mhz 100 pf q g total gate charge v gs =-4.5v, i d =-1a, v ds =-6v 9.0 nc v sd diode forward voltage i s =-1a, v gs =0v -0.71 v t rr source-drain reverse recovery time i s =-1a, v gs =0v, di/dt=100a/s 40 ns r ds (o n ) 9/14/03 rev5 TS8405P 3 9/14/03 rev5 TS8405P 4 9/14/03 rev5 TS8405P 5 9/14/03 rev5 TS8405P 6 9/14/03 rev5 TS8405P TS8405P 7 9/14/03 rev5 TS8405P 8 9/14/03 rev5 TS8405P 9 9/14/03 rev5 TS8405P 10 9/14/03 rev5 TS8405P 11 9/14/03 rev5 dimensional outline and pad layout TS8405P preliminary data sheet 0.80mm 0.80mm ? 0.30mm solder mask ? ~ 0.40mm land pattern recommendation dd s g d = drain pad s = source pad g = gate pad silicon 0.80mm max 0.27mm 0.80mm 1.50mm 0.80mm 0.35mm 0.35mm bump ? 0.37mm 1.50mm 11 exxxx backside view (no bump side view) mark on backside of die e = 8405p product code xxxx = lot traceability code mark is located in lower right quadrant on top of source pad. gate pad is located in lower left quadrant. bumps are eutectic solder 63/37 sn/pb 9/14/03 rev5 |
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